Added new options:
--get-offsets-terse --get-physical-cores --set-pbo-scalar --get-pbo-scalar Presumably fixed compatibility with SKUs that have disabled physical cores Presumably have a "clean" exit if the program is run on an unsupported system
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GPG Key ID:
E71F77DDBC513FD7
@ -1,12 +1,29 @@
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using System.CommandLine;
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using System.Management;
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using ZenStates.Core;
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using System.Security.Principal;
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namespace ryzen_smu_cli
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{
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class Program
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{
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private static readonly Cpu ryzen = new();
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private static readonly Cpu ryzen;
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private static readonly Dictionary<int, int> mappedCores;
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static Program()
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{
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try
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{
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ryzen = new Cpu();
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}
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catch (Exception ex)
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{
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Console.WriteLine($"Error: {ex.Message}");
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Console.WriteLine("If the previous message was unclear, for some reason, ZenStates-Core failed to initialize an instance of the CPU control object.");
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Environment.Exit(1);
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}
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mappedCores = MapLogicalCoresToPhysical();
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}
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private static readonly string wmiAMDACPI = "AMD_ACPI";
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private static readonly string wmiScope = "root\\wmi";
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@ -19,19 +36,37 @@ namespace ryzen_smu_cli
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private static bool wmiPopulated = false;
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private static bool rebootFlag = false;
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static int Main(string[] args)
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{
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if (!IsAdministrator())
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{
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Console.WriteLine("This application must be run as an administrator.");
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Environment.Exit(1);
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}
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var rootCommand = new RootCommand("A CLI for the Ryzen SMU.");
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var pboOffset = new Option<string>("--offset", "Specify a zero-indexed core, or list of cores, and their PBO offset(s), in a fashion similar to taskset. e.g. 0:-10,1:5,2:-20,14:-25");
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var disableCores = new Option<string>("--disable-cores", "Specify a zero-indexed list of cores to disable. e.g. 0,1,4,7,12,15. This setting does not take into account any current core disablement. All cores you wish to disable must be specified. Any that are unspecified will be enabled. This option requires a reboot.");
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var pboOffset = new Option<string>("--offset", "Specify a zero-indexed logical core, or list of logical cores, and their PBO offset(s), in a fashion similar to taskset. e.g. 0:-10,1:5,2:-20,14:-25. These are the logical core IDs as they appear in your system, not the true IDs according to fused hardware disabled cores.");
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var disableCores = new Option<string>("--disable-cores", "Specify a zero-indexed list of logical cores to disable. e.g. 0,1,4,7,12,15. This setting does not take into account any current core disablement. All cores you wish to disable must be specified. Any that are unspecified will be enabled. This option requires a reboot.");
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var enableCores = new Option<bool>("--enable-all-cores", "Enable all cores.");
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//var toggleJson = new Option<bool>("--json", "Enable json format for informational outputs.");
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var getCurrentPBOTerse = new Option<bool>("--get-offsets-terse", "Print a list of all PBO offsets on logical cores in a simple, comma-separated format, without core identifiers. e.g. -15,0,2,-20.");
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var getPhysicalCores = new Option<bool>("--get-physical-cores", "Print a list of physical cores, to find out which ones are disabled in <8-core-per-CCD SKUs.");
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var setPBOScalar = new Option<string>("--set-pbo-scalar", "Sets the PBO scalar. This is a whole number between 1 and 10.");
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var getPBOScalar = new Option<bool>("--get-pbo-scalar", "Get the current PBO scalar.");
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rootCommand.AddOption(pboOffset);
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rootCommand.AddOption(disableCores);
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rootCommand.AddOption(enableCores);
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rootCommand.AddOption(getCurrentPBOTerse);
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rootCommand.AddOption(getPhysicalCores);
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rootCommand.AddOption(setPBOScalar);
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rootCommand.AddOption(getPBOScalar);
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rootCommand.SetHandler((offsetArgs, coreDisableArgs, enableAll) =>
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rootCommand.SetHandler((offsetArgs, coreDisableArgs, enableAll, getCurrentPBOTerse, getPhysicalCores,
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setPBOScalar, getPBOScalar) =>
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{
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if (!string.IsNullOrEmpty(offsetArgs)) ApplyPBOOffset(offsetArgs);
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@ -39,8 +74,35 @@ namespace ryzen_smu_cli
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if (enableAll) ApplyDisableCores();
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}, pboOffset, disableCores, enableCores);
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if (getCurrentPBOTerse)
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{
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Console.WriteLine("Current PBO offsets:");
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string offsetLine = "";
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for (int i = 0; i < mappedCores.Count; i++)
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{
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int mapIndex = i < 8 ? 0 : 1;
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uint coreMask = ryzen.MakeCoreMask((uint)mappedCores[i]);
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offsetLine += Convert.ToDecimal((int)ryzen.GetPsmMarginSingleCore((uint)(((mapIndex << 8) | ((mappedCores[i] % 8) & 0xF)) << 20)));
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offsetLine += ",";
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}
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Console.WriteLine(offsetLine.TrimEnd(','));
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}
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if (getPhysicalCores)
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{
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Console.WriteLine("Fused status of physical cores:");
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for (var i = 0; i < ryzen.info.topology.physicalCores; i++)
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{
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int mapIndex = i < 8 ? 0 : 1;
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if ((~ryzen.info.topology.coreDisableMap[mapIndex] >> i % 8 & 1) == 0) Console.WriteLine($"Core {i}: Disabled");
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else Console.WriteLine($"Core {i}: Enabled");
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}
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}
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if (!string.IsNullOrEmpty(setPBOScalar)) ryzen.SetPBOScalar(Convert.ToUInt32(setPBOScalar));
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if (getPBOScalar) Console.WriteLine($"Current PBO scalar: {ryzen.GetPBOScalar()}");
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}, pboOffset, disableCores, enableCores, getCurrentPBOTerse, getPhysicalCores, setPBOScalar, getPBOScalar);
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if (args.Length == 0)
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{
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@ -59,6 +121,25 @@ namespace ryzen_smu_cli
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return 0;
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}
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private static Dictionary<int, int> MapLogicalCoresToPhysical()
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{
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Dictionary<int, int> mappedCores = [];
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int logicalCoreIter = 0;
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for (var i = 0; i < ryzen.info.topology.physicalCores; i++)
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{
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int mapIndex = i < 8 ? 0 : 1;
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if ((~ryzen.info.topology.coreDisableMap[mapIndex] >> i % 8 & 1) != 0)
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{
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mappedCores.Add(logicalCoreIter, i);
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logicalCoreIter += 1;
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}
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}
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return mappedCores;
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}
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private static string GetWmiInstanceName()
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{
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try
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@ -127,28 +208,27 @@ namespace ryzen_smu_cli
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private static void ApplyPBOOffset(string offsetArgs)
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{
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string[] arg = offsetArgs.Split(',');
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for (int i = 0; i < arg.Length; i++)
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// This checks if the current SKU has a known register for writing PBO offsets
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if (ryzen.smu.Rsmu.SMU_MSG_SetDldoPsmMargin != 0)
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{
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int core = Convert.ToInt32(arg[i].Split(':')[0]);
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int offset = Convert.ToInt32(arg[i].Split(':')[1]);
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string[] arg = offsetArgs.Split(',');
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// var unavailableCoreMap = MapUnavailableCores();
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// Magic numbers from SMUDebugTool
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// This does some bitshifting calculations to get the mask for individual cores for chips with up to two CCDs
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// I'm not sure if it would work with more, in theory. It's unclear to me based on the github issues.
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int mapIndex = core < 8 ? 0 : 1;
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if ((~ryzen.info.topology.coreDisableMap[mapIndex] >> core % 8 & 1) == 1)
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for (int i = 0; i < arg.Length; i++)
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{
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ryzen.SetPsmMarginSingleCore((uint)(((mapIndex << 8) | core % 8 & 0xF) << 20), offset);
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Console.WriteLine($"Set core {core} offset to {offset}!");
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}
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int core = Convert.ToInt32(arg[i].Split(':')[0]);
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int offset = Convert.ToInt32(arg[i].Split(':')[1]);
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else
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{
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Console.WriteLine($"Unable to set offset on disabled core {core}.");
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// Magic numbers from SMUDebugTool
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// This does some bitshifting calculations to get the mask for individual cores for chips with up to two CCDs
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// Support for threadrippers/epyc is theoretically available, if the calculations were expanded, but are untested
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int mapIndex = core < 8 ? 0 : 1;
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ryzen.SetPsmMarginSingleCore((uint)(((mapIndex << 8) | mappedCores[core] % 8 & 0xF) << 20), offset);
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Console.WriteLine($"Set logical core {core} offset to {offset}!");
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}
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}
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else Console.WriteLine("You have attempted to enable PBO offsets on a CPU that does not support them.");
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}
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private static void ApplyDisableCores(string coreArgs = "Enable")
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@ -191,5 +271,14 @@ namespace ryzen_smu_cli
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Console.WriteLine("Something has gone terribly wrong, the downcore config option is not present.");
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}
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}
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private static bool IsAdministrator()
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{
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using (WindowsIdentity identity = WindowsIdentity.GetCurrent())
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{
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WindowsPrincipal principal = new WindowsPrincipal(identity);
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return principal.IsInRole(WindowsBuiltInRole.Administrator);
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}
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}
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}
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}
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@ -6,7 +6,7 @@
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<RootNamespace>ryzen_smu_cli</RootNamespace>
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<ImplicitUsings>enable</ImplicitUsings>
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<Nullable>enable</Nullable>
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<Version>0.0.2</Version>
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<Version>0.1.0</Version>
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</PropertyGroup>
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<PropertyGroup>
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