rawhide_k/ryzen-smu-cli
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Moved admin check to the correct location

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Fixed bugs in using the core map to set offsets
Refactored the core map to account for disabled cores on any SKU
Catch exception when fetching offsets when a core is disabled
Added input validation to --offset, and added terse input notation
Added --get-enabled-cores to print a list of logically enabled cores
This commit is contained in:
rawhide kobayashi 2025-04-01 17:55:06 -05:00
parent 9ebbdfc47f
commit fe26e9dc75
Signed by: rawhide_k
GPG Key ID: E71F77DDBC513FD7
2 changed files with 78 additions and 22 deletions
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98
ryzen-smu-cli/Program.cs
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@ -2,6 +2,7 @@
using System.Management;
using ZenStates.Core;
using System.Security.Principal;
using System.Text.RegularExpressions;
namespace ryzen_smu_cli
{
@ -11,6 +12,12 @@ namespace ryzen_smu_cli
private static readonly Dictionary<int, int> mappedCores;
static Program()
{
if (!IsAdministrator())
{
Console.WriteLine("This application must be run as an administrator.");
Environment.Exit(1);
}
try
{
ryzen = new Cpu();
@ -36,8 +43,6 @@ namespace ryzen_smu_cli
private static bool wmiPopulated = false;
private static bool rebootFlag = false;
static int Main(string[] args)
{
if (!IsAdministrator())
@ -48,12 +53,13 @@ namespace ryzen_smu_cli
var rootCommand = new RootCommand("A CLI for the Ryzen SMU.");
var pboOffset = new Option<string>("--offset", "Specify a zero-indexed logical core, or list of logical cores, and their PBO offset(s), in a fashion similar to taskset. e.g. 0:-10,1:5,2:-20,14:-25. These are the logical core IDs as they appear in your system, not the true IDs according to fused hardware disabled cores.");
var pboOffset = new Option<string>("--offset", "Specify a zero-indexed logical core, or list of logical cores, and their PBO offset(s), in a fashion similar to taskset. e.g. 0:-10,1:5,2:-20,14:-25. These are the logical core IDs as they appear in your system, not the true IDs according to fused hardware disabled cores. Alternatively, you may supply a simpler comma-separated list of offset values - e.g. 0,-14,-30,5,-10,-22 - but, obviously, this can only set the value on up to X core that you define.");
var disableCores = new Option<string>("--disable-cores", "Specify a zero-indexed list of logical cores to disable. e.g. 0,1,4,7,12,15. This setting does not take into account any current core disablement. All cores you wish to disable must be specified. Any that are unspecified will be enabled. This option requires a reboot.");
var enableCores = new Option<bool>("--enable-all-cores", "Enable all cores.");
//var toggleJson = new Option<bool>("--json", "Enable json format for informational outputs.");
var getCurrentPBOTerse = new Option<bool>("--get-offsets-terse", "Print a list of all PBO offsets on logical cores in a simple, comma-separated format, without core identifiers. e.g. -15,0,2,-20.");
var getCurrentPBOTerse = new Option<bool>("--get-offsets-terse", "Print a list of all PBO offsets on logical cores in a simple, comma-separated format, without core identifiers. e.g. -15,0,2,-20. Note that you cannot retrieve the offsets from disabled cores.");
var getPhysicalCores = new Option<bool>("--get-physical-cores", "Print a list of physical cores, to find out which ones are disabled in <8-core-per-CCD SKUs.");
var getEnabledCores = new Option<bool>("--get-enabled-cores", "Print a list of logically enabled/disabled cores, and their relationship to the physical cores, inclusive of factory-fused disabled cores.");
var setPBOScalar = new Option<string>("--set-pbo-scalar", "Sets the PBO scalar. This is a whole number between 1 and 10.");
var getPBOScalar = new Option<bool>("--get-pbo-scalar", "Get the current PBO scalar.");
@ -62,10 +68,11 @@ namespace ryzen_smu_cli
rootCommand.AddOption(enableCores);
rootCommand.AddOption(getCurrentPBOTerse);
rootCommand.AddOption(getPhysicalCores);
rootCommand.AddOption(getEnabledCores);
rootCommand.AddOption(setPBOScalar);
rootCommand.AddOption(getPBOScalar);
rootCommand.SetHandler((offsetArgs, coreDisableArgs, enableAll, getCurrentPBOTerse, getPhysicalCores,
rootCommand.SetHandler((offsetArgs, coreDisableArgs, enableAll, getCurrentPBOTerse, getEnabledCores, getPhysicalCores,
setPBOScalar, getPBOScalar) =>
{
if (!string.IsNullOrEmpty(offsetArgs)) ApplyPBOOffset(offsetArgs);
@ -78,15 +85,27 @@ namespace ryzen_smu_cli
{
Console.WriteLine("Current PBO offsets:");
string offsetLine = "";
bool flagNotifyDisabledCCD = false;
for (int i = 0; i < mappedCores.Count; i++)
{
int mapIndex = i < 8 ? 0 : 1;
uint coreMask = ryzen.MakeCoreMask((uint)mappedCores[i]);
offsetLine += Convert.ToDecimal((int)ryzen.GetPsmMarginSingleCore((uint)(((mapIndex << 8) | ((mappedCores[i] % 8) & 0xF)) << 20)));
offsetLine += ",";
try
{
offsetLine += Convert.ToDecimal((int)ryzen.GetPsmMarginSingleCore((uint)(((mapIndex << 8) | ((mappedCores[i] % 8) & 0xF)) << 20)));
offsetLine += ",";
}
catch (InvalidOperationException)
{
// This will occur if a CCD is disabled through BIOS e.g. with TURBO GAMER MODE.
// But it's not a real problem.
flagNotifyDisabledCCD = true;
}
}
Console.WriteLine(offsetLine.TrimEnd(','));
if (flagNotifyDisabledCCD) Console.WriteLine("You have manually disabled cores. It is not possible to retrieve offset values while they are disabled.");
}
if (getPhysicalCores)
@ -100,9 +119,18 @@ namespace ryzen_smu_cli
}
}
if (getEnabledCores)
{
for (var i = 0; i < ryzen.info.topology.physicalCores; i++)
{
if (mappedCores.ContainsValue(i)) Console.WriteLine($"Core {i}: Enabled");
else Console.WriteLine($"Core {i}: Disabled");
}
}
if (!string.IsNullOrEmpty(setPBOScalar)) ryzen.SetPBOScalar(Convert.ToUInt32(setPBOScalar));
if (getPBOScalar) Console.WriteLine($"Current PBO scalar: {ryzen.GetPBOScalar()}");
}, pboOffset, disableCores, enableCores, getCurrentPBOTerse, getPhysicalCores, setPBOScalar, getPBOScalar);
}, pboOffset, disableCores, enableCores, getCurrentPBOTerse, getEnabledCores, getPhysicalCores, setPBOScalar, getPBOScalar);
if (args.Length == 0)
{
@ -130,7 +158,7 @@ namespace ryzen_smu_cli
for (var i = 0; i < ryzen.info.topology.physicalCores; i++)
{
int mapIndex = i < 8 ? 0 : 1;
if ((~ryzen.info.topology.coreDisableMap[mapIndex] >> i % 8 & 1) != 0)
if (ryzen.GetPsmMarginSingleCore((uint)(((mapIndex << 8) | ((i % 8) & 0xF)) << 20)) != null)
{
mappedCores.Add(logicalCoreIter, i);
logicalCoreIter += 1;
@ -211,21 +239,49 @@ namespace ryzen_smu_cli
// This checks if the current SKU has a known register for writing PBO offsets
if (ryzen.smu.Rsmu.SMU_MSG_SetDldoPsmMargin != 0)
{
string[] arg = offsetArgs.Split(',');
// var unavailableCoreMap = MapUnavailableCores();
string validArgFormat = @"^(-?\d{1,2}(,-?\d{1,2})*|\d{1,2}:-?\d{1,2}(,\d{1,2}:-?\d{1,2})*)$";
for (int i = 0; i < arg.Length; i++)
if (Regex.IsMatch(offsetArgs, validArgFormat))
{
int core = Convert.ToInt32(arg[i].Split(':')[0]);
int offset = Convert.ToInt32(arg[i].Split(':')[1]);
string[] arg = offsetArgs.Split(',');
// Magic numbers from SMUDebugTool
// This does some bitshifting calculations to get the mask for individual cores for chips with up to two CCDs
// Support for threadrippers/epyc is theoretically available, if the calculations were expanded, but are untested
int mapIndex = core < 8 ? 0 : 1;
ryzen.SetPsmMarginSingleCore((uint)(((mapIndex << 8) | mappedCores[core] % 8 & 0xF) << 20), offset);
Console.WriteLine($"Set logical core {core} offset to {offset}!");
if (arg.Length <= mappedCores.Count)
{
for (int i = 0; i < arg.Length; i++)
{
// Magic numbers from SMUDebugTool
// This does some bitshifting calculations to get the mask for individual cores for chips with up to two CCDs
// Support for threadrippers/epyc is theoretically available, if the calculations were expanded, but are untested
try
{
int mapIndex = mappedCores[i] < 8 ? 0 : 1;
if (arg[i].Contains(':'))
{
int core = Convert.ToInt32(arg[i].Split(':')[0]);
int offset = Convert.ToInt32(arg[i].Split(':')[1]);
ryzen.SetPsmMarginSingleCore((uint)(((mapIndex << 8) | mappedCores[core] % 8 & 0xF) << 20), offset);
Console.WriteLine($"Set logical core {core}, physical core {mappedCores[core]} offset to {offset}!");
}
else
{
ryzen.SetPsmMarginSingleCore((uint)(((mapIndex << 8) | mappedCores[i] % 8 & 0xF) << 20), Convert.ToInt32(arg[i]));
Console.WriteLine($"Set logical core {i}, physical core {mappedCores[i]} offset to {arg[i]}!");
}
}
catch (KeyNotFoundException)
{
Console.WriteLine($"Tried to set an offset on logical core {Convert.ToInt32(arg[i].Split(':')[0])}, but there are only {mappedCores.Count} (zero-indexed, as a reminder) logical cores active in the system.");
}
}
}
else Console.WriteLine("Specified a greater number of offsets than logical cores active in the system. Please check and try again.");
}
else Console.WriteLine("Malformed input format for offsets. Please check and try again.");
}
else Console.WriteLine("You have attempted to enable PBO offsets on a CPU that does not support them.");

2
ryzen-smu-cli/ryzen-smu-cli.csproj
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@ -6,7 +6,7 @@
<RootNamespace>ryzen_smu_cli</RootNamespace>
<ImplicitUsings>enable</ImplicitUsings>
<Nullable>enable</Nullable>
<Version>0.1.0</Version>
<Version>0.1.1</Version>
</PropertyGroup>
<PropertyGroup>