Merge pull request #12 from sp00n/master

This should fix #11 (--get-offsets-terse not displaying the correct values for some cores)

README.md

@@ -8,7 +8,7 @@ All credit to irusanov, who wrote [ZenStates-Core](https://github.com/irusanov/Z
 
 Usage:
 ```
-.\ryzen-smu-cli.exe --help
+PS G:\win-x64> .\ryzen-smu-cli.exe --help
 Description:
   A CLI for the Ryzen SMU.
 
@@ -16,11 +16,24 @@ Usage:
   ryzen-smu-cli [options]
 
 Options:
-  --offset <offset>                  Specify a zero-indexed logical core, or list of logical cores, and their PBO offset(s), in a fashion similar to taskset. e.g. 0:-10,1:5,2:-20,14:-25. These are the logical core IDs as they appear in your system, not the true IDs according to fused hardware disabled cores.
+  --offset <offset>                  Specify a zero-indexed logical core, or list of logical cores, and their PBO
-  --disable-cores <disable-cores>    Specify a zero-indexed list of logical cores to disable. e.g. 0,1,4,7,12,15. This setting does not take into account any current core disablement. All cores you wish to disable must be specified. Any that are unspecified will be enabled. This option requires a reboot.
+                                     offset(s), in a fashion similar to taskset. e.g. 0:-10,1:5,2:-20,14:-25. These are
+                                     the logical core IDs as they appear in your system, not the true IDs according to
+                                     fused hardware disabled cores. Alternatively, you may supply a simpler
+                                     comma-separated list of offset values - e.g. 0,-14,-30,5,-10,-22 - but, obviously,
+                                     this can only set the value on up to X core that you define.
+  --disable-cores <disable-cores>    Specify a zero-indexed list of logical cores to disable. e.g. 0,1,4,7,12,15. This
+                                     setting does not take into account any current core disablement. All cores you
+                                     wish to disable must be specified. Any that are unspecified will be enabled. This
+                                     option requires a reboot.
   --enable-all-cores                 Enable all cores.
-  --get-offsets-terse                Print a list of all PBO offsets on logical cores in a simple, comma-separated format, without core identifiers. e.g. -15,0,2,-20.
+  --get-offsets-terse                Print a list of all PBO offsets on logical cores in a simple, comma-separated
-  --get-physical-cores               Print a list of physical cores, to find out which ones are disabled in <8-core-per-CCD SKUs.
+                                     format, without core identifiers. e.g. -15,0,2,-20. Note that you cannot retrieve
+                                     the offsets from disabled cores.
+  --get-physical-cores               Print a list of physical cores, to find out which ones are disabled in
+                                     <8-core-per-CCD SKUs.
+  --get-enabled-cores                Print a list of logically enabled/disabled cores, and their relationship to the
+                                     physical cores, inclusive of factory-fused disabled cores.
   --set-pbo-scalar <set-pbo-scalar>  Sets the PBO scalar. This is a whole number between 1 and 10.
   --get-pbo-scalar                   Get the current PBO scalar.
   --version                          Show version information

ryzen-smu-cli/Program.cs

@@ -79,12 +79,18 @@ namespace ryzen_smu_cli
                     Console.WriteLine("Current PBO offsets:");
                     string offsetLine = "";
                     bool flagNotifyDisabledCCD = false;
-                    for (int i = 0; i < mappedCores.Count; i++)
+
+                    for (int logicalCore = 0; logicalCore < mappedCores.Count; logicalCore++)
                     {
-                        int mapIndex = i < 8 ? 0 : 1;
+                        int physicalCore = mappedCores[logicalCore];
+                        int ccdIndex = (int)Math.Floor((double)(physicalCore / 8));
+                        int ccdBitMask = ccdIndex << 8;
+                        int coreNumOnCcd = physicalCore % 8;
+                        uint coreBitMask = (uint)((ccdBitMask | (coreNumOnCcd & 0xF)) << 20);
+
                         try
                         {
-                            offsetLine += Convert.ToDecimal((int)ryzen.GetPsmMarginSingleCore((uint)(((mapIndex << 8) | ((mappedCores[i] % 8) & 0xF)) << 20))!);
+                            offsetLine += Convert.ToDecimal((int)ryzen.GetPsmMarginSingleCore(coreBitMask)!);
                             offsetLine += ",";
                         }
 

ryzen-smu-cli/ryzen-smu-cli.csproj

@@ -6,7 +6,7 @@
     <RootNamespace>ryzen_smu_cli</RootNamespace>
     <ImplicitUsings>enable</ImplicitUsings>
     <Nullable>enable</Nullable>
-    <Version>0.1.2</Version>
+    <Version>0.1.3</Version>
   </PropertyGroup>
 
   <PropertyGroup>